{"id":24457,"date":"2020-02-26T17:42:56","date_gmt":"2020-02-26T12:12:56","guid":{"rendered":"https:\/\/kseebsolutions.guru\/?p=24457"},"modified":"2021-07-02T15:24:09","modified_gmt":"2021-07-02T09:54:09","slug":"2nd-puc-electronics-question-bank-chapter-10","status":"publish","type":"post","link":"https:\/\/kseebsolutions.guru\/2nd-puc-electronics-question-bank-chapter-10\/","title":{"rendered":"2nd PUC Electronics Question Bank Chapter 10 Digital Electronics"},"content":{"rendered":"

Students can Download 2nd PUC Electronics Chapter 10 Digital Electronics Questions and Answers, Notes Pdf, 2nd PUC Electronics Question Bank with Answers<\/a>\u00a0helps you to revise the complete Karnataka State Board Syllabus and score more marks in your examinations.<\/p>\n

Karnataka 2nd PUC Electronics Question Bank Chapter 10 Digital Electronics<\/h2>\n

2nd PUC Electronics Digital Electronics One Mark Questions and Answers<\/h3>\n

Question 1.
\nWhat is an XOR gate?
\nAnswer:
\nThe logic gate whose output is high only when odd number of inputs are high is known as an XOR gate<\/p>\n

Question 2.
\nDraw the symbol of XOR gate?
\nAnswer:
\n\"2nd<\/p>\n

Question 3.
\nWrite the Boolean equation of XOR gate
\nAnswer:
\n\\(\\mathrm{Y}=\\mathrm{A} \\overline{\\mathrm{B}}+\\overline{\\mathrm{A}} \\mathrm{B}=\\mathrm{A} \\oplus \\mathrm{B}\\)<\/p>\n

\"2nd<\/p>\n

Question 4.
\nDraw the symbol of XOR gate.
\nAnswer:<\/p>\n\n\n\n\n\n\n\n\n
Input<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
A<\/strong><\/td>\nB<\/strong><\/td>\nY= A \u2295 B<\/strong><\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 5.
\nDraw the symbol of XNOR gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 6.
\nWrite the Boolean expression for the XNOR gate.
\nAnswer:
\n\\(\\mathrm{Y}=\\mathrm{AB}+\\overline{\\mathrm{A}} \\overline{\\mathrm{B}} =\\overline{\\mathrm{A} \\oplus \\mathrm{B}}\\)<\/p>\n

Question 7.
\nWrite the truth table of XNOR gate
\nAnswer:<\/p>\n\n\n\n\n\n\n\n\n
Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
A<\/td>\nB<\/td>\n\\(\\mathrm{Y}=\\overline{\\mathrm{A} \\oplus \\mathrm{B}}\\)<\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 8.
\nName the universal gates.
\nAnswer:
\nNAND gate and NOR gate.<\/p>\n

Question 9.
\nHow many two input NAND gates are required to produce two input OR function?
\nAnswer:
\nThree.<\/p>\n

Question 10.
\nHow many two input NOR gates must be used to produce two input OR function?
\nAnswer:
\nTwo.<\/p>\n

Question 11.
\nWhy do we use digital codes?
\nAnswer:
\nDigital codes are used to represent analog information.<\/p>\n

Question 12.
\nWhat is BCD code?
\nAnswer:
\nBCD is a numeric code in which each digit of a decimal number is represented by a four bit binary number.<\/p>\n

\"2nd<\/p>\n

Question 13.
\nWhat is a gray code?
\nAnswer:
\nGray code is a non-weighted code which is used in analog to digital conversion.<\/p>\n

Question 14.
\nWhich are weighted codes?
\nAnswer:
\n8421 code, 2421 code.<\/p>\n

Question 15.
\nWhich are non-weighted codes?
\nAnswer:
\nExcess-3 code, Gray code.<\/p>\n

Question 16.
\nName the self complementing code.
\nAnswer:
\nExcess-3 code.<\/p>\n

Question 17.
\nConvert 11012<\/sub> into gray code.
\nAnswer:
\n\"2nd<\/p>\n

Question 18.
\nName the alpha numeric codes.
\nAnswer:
\nASCII code, EBCDIC code.<\/p>\n

Question 19.
\nExpand ASCII.
\nAnswer:
\nAmerican Standard code for Information Interchange.<\/p>\n

Question 20.
\nExpand EBCDIC.
\nAnswer:
\nExtended Binary Coded Decimal Interchange Code.<\/p>\n

Question 21.
\nHow many zone bits are there in EBCDIC?
\nAnswer:
\n4<\/p>\n

\"2nd<\/p>\n

Question 22.
\nWhat is a half-adder?
\nAnswer:
\nHalf adder is a logic circuit which adds two bits and gives to outputs sum and carry.<\/p>\n

Question 23.
\nWhat is a full adder?
\nAnswer:
\nFull adder is a combinational logic circuit that performs arithmetic sum of three input bits and gives as output sum and carry.<\/p>\n

Question 24.
\nWhat is a half subtractor?
\nAnswer:
\nHalf subtractor is a combinational logic circuit which performs the subtraction of two bits and gives difference and borrow.<\/p>\n

Question 25.
\nDraw the block diagram of half adder.
\nAnswer:
\n\"2nd<\/p>\n

Question 26.
\nDraw the block diagram of full adder.
\nAnswer:
\n\"2nd<\/p>\n

Question 27.
\nDraw the block diagram of half subtractor
\nAnswer:
\n\"2nd<\/p>\n

Question 28.
\nWrite the Boolean expression for sum of half adder.
\nAnswer:
\n\\(A \\oplus B=A \\bar{B}+\\bar{A} B\\)<\/p>\n

Question 29.
\nWrite the Boolean expression for sum of full adder.
\nAnswer:
\nA \u2295 B \u2295 Cin<\/sub>.<\/p>\n

\"2nd<\/p>\n

Question 30.
\nWrite the Boolean expression for the carry of half adder.
\nAnswer:
\nAB.<\/p>\n

Question 31.
\nWrite the Boolean expression for the carry of full adder.
\nAnswer:
\nCo<\/sub> = AB + BCin<\/sub> + Cin<\/sub> A.<\/p>\n

Question 32.
\nWrite the Boolean expression for difference of half subtractor.
\nAnswer:
\nA \u2295 B<\/p>\n

Question 33.
\nWrite the Boolean expression for borrow of half subtractor.
\nAnswer:
\n\\(\\overline{\\mathrm{A}} \\mathrm{B}\\)<\/p>\n

Question 34.
\nDefine min term.
\nAnswer:
\nMin term is a special case product (AND) term containing all the input variables that make up a Boolean expression.<\/p>\n

Question 35.
\nDefine max term.
\nAnswer:
\nMax term is a special case sum (OR) term containing all the input variables that make up a Boolean expression.<\/p>\n

Question 36.
\nDefine SOP.
\nAnswer:
\nThe Boolean expression containing all input variables in each of product term either in complemented or uncomplemented form is known as canonical sum of products expression.<\/p>\n

\"2nd<\/p>\n

Question 37.
\nDefine POS.
\nAnswer:
\nThe Boolean expression containing all the input variables either in complemented or uncomplemented form in each of sum term is known as canonical POS expression.<\/p>\n

Question 38.
\nWhat is canonical SOP equation?
\nAnswer:
\nIt is an equation containing all input variables in each of product term either in complemented or uncomplemented form.<\/p>\n

Question 39.
\nWhat is canonical POS equation?
\nAnswer:
\nIt is an equation containing all input variables either in complemented or uncomplemented form in each of sum term.<\/p>\n

Question 40.
\nWhat is a Karnaugh map?
\nAnswer:
\nKarnaugh map is a graphical method of simplification of Boolean expression.<\/p>\n

Question 41.
\nWhat is meant by looping?
\nAnswer:
\nLooping is encircling of two adjacent 1 s on a K map.<\/p>\n

Question 42.
\nWhat is a cell in K map?
\nAnswer:
\nA cell in a K map is a box which represents a particular combination of variables in its product form.<\/p>\n

Question 43.
\nWhat is meant by redundant group?
\nAnswer:
\nA redundant group is a group in which all the 1 s in a group are over lapped by other groups.<\/p>\n

Question 44.
\nWhat is a pair?
\nAnswer:
\nA group of adjacent 1 either horizontally or vertically but not diagonally on a K map is called a pair.<\/p>\n

Question 45.
\nWhat is a quad?
\nAnswer:
\nQuad is a group of four adjacent 1 s in a K-map.<\/p>\n

\"2nd<\/p>\n

Question 46.
\nWhat is an octet?
\nAnswer:
\nAn octet is a group of eight adjacent Is either in two rows or two columns in a K map.<\/p>\n

Question 47.
\nHow many variables does the pair eliminate?
\nAnswer:
\nOne variable.<\/p>\n

Question 48.
\nHow many variables does the quad eliminate?
\nAnswer:
\nTwo variables.<\/p>\n

Question 49.
\nHow many variables does the octet eliminate?
\nAnswer:
\nThree variables.<\/p>\n

Question 50.
\nWhat is a don\u2019t care condition?
\nAnswer:
\nAn output condition that may be either 1 or 0 without affecting the operation of the system is called don\u2019t care condition.<\/p>\n

Question 51.
\nName the universal gate used to realize AND-OR logic.
\nAnswer:
\nNAND gate.<\/p>\n

\"2nd<\/p>\n

Question 52.
\nName the universal gate used to realize OR-AND logic.
\nAnswer:
\nNOR gate<\/p>\n

Question 53.
\nWhat is a sequential logic circuit?
\nAnswer:
\nSequential logic circuits are those circuits whose output level depends on present levels of input and previous input levels.<\/p>\n

Question 54.
\nWhat is a flip flop?
\nAnswer:
\nA flip flop is a bistable multivibrator which has two stable states. It is a basic memory element which can store one bit information.<\/p>\n

Question 55.
\nIs the flip flop a bistable device?
\nAnswer:
\nYes Flip flop is a bistable device.<\/p>\n

Question 56.
\nDefine a clock pulse.
\nAnswer:
\nA clock is a periodic train of pulses or square waves which acts as a control signal. The output changes state only when clock makes transition.<\/p>\n

Question 57.
\nDraw the logic circuit of an unclocked SR flip flop.
\nAnswer:
\n\"2nd<\/p>\n

Question 58
\nDraw the logic diagram of a D flip flop.
\nAnswer:
\n\"2nd<\/p>\n

\"2nd<\/p>\n

Question 59.
\nDraw the logic diagram of a JK flip flop.
\nAnswer:
\n\"2nd<\/p>\n

Question 60.
\nDraw the logic diagram of T nip flop.
\nAnswer:
\n\"2nd<\/p>\n

Question 61.
\nWhat is a register?
\nAnswer:
\nA register is a set of flip flops used to store binary data.<\/p>\n

Question 62.
\nWhich is the line used to transfer data in and out of a PISO shift register?
\nAnswer:
\nThe SHIFT LOAD line.<\/p>\n

Question 63.
\nWhat is a counter?
\nAnswer:<\/p>\n

2nd PUC Electronics Digital Electronics Two Marks Questions and Answers<\/h3>\n

Question 1.
\nWhat is an XOR gate? Write its truth table.
\nAnswer:
\nXOR gate is a logic gate whose output is HIGH only when odd number of inputs are HIGH.<\/p>\n\n\n\n\n\n\n\n\n
Input<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
A<\/strong><\/td>\nB<\/strong><\/td>\nY = A + B<\/strong><\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 2.
\nWhat is an XNOR gate? Write its truth table.
\nAnswer:
\nXNOR gate is a logic circuit whose output is HIGH only the inputs are same<\/p>\n\n\n\n\n\n\n\n\n
Input<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
A<\/strong><\/td>\nB<\/strong><\/td>\nY = A + B<\/strong><\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"2nd<\/p>\n

Question 3.
\nDraw the pin diagram of IC 7400.
\nAnswer:
\n\"2nd<\/p>\n

Question 4.
\nDraw the pin diagram of IC 7402.
\nAnswer:
\n\"2nd
\nQuestion 5.
\nExplain the term universal gates.
\nAnswer:
\nNAND gate and NOR gate are called universal gates because all the logic gates can be realised using these gates.<\/p>\n

Question 6.
\nRealise XNOR gate using only NOR gates.
\nAnswer:
\n\"2nd<\/p>\n

Question 7.
\nWhat is the most important characteristic of gray code? Explain.
\nAnswer:
\nGray code changes only by one bit, each time the decimal number is incremented.<\/p>\n\n\n\n\n\n\n\n\n\n
Decimal digit<\/strong><\/td>\nBCD<\/strong><\/td>\nGray<\/strong><\/td>\n<\/tr>\n
0<\/td>\n0000<\/td>\n0000<\/td>\n<\/tr>\n
1<\/td>\n0001<\/td>\n0001<\/td>\n<\/tr>\n
2<\/td>\n0010<\/td>\n0011<\/td>\n<\/tr>\n
3<\/td>\n0011<\/td>\n0010<\/td>\n<\/tr>\n
4<\/td>\n0100<\/td>\n0110<\/td>\n<\/tr>\n
5<\/td>\n0101<\/td>\n0111<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 8.
\nDistinguish between excess-3 code and BCD code
\nAnswer:
\nExcess-3 code is a non-weighted self complementing code. It is obtained by adding 3 to each digit in decimal number. BCD code is a weighted code. Each decimal number is represented by a separate group of four bits.<\/p>\n

\"2nd<\/p>\n

Question 9.
\nConvert gray code 1000 into binary using XOR
\nAnswer:
\n\"2nd<\/p>\n

Question 10.
\nDistingish between half adder and full adder.
\nAnswer:
\nFull adder is combinational circuit which adds three bits and gives sum and carry. Half adder adds two bits and gives sum and carry.<\/p>\n

Question 11.
\nWrite the truth table and draw the timing diagram of a half adder.
\nAnswer:<\/p>\n\n\n\n\n\n\n\n\n
Inputs<\/strong><\/td>\nOutputs<\/strong><\/td>\n<\/tr>\n
A<\/strong><\/td>\nB<\/strong><\/td>\nSum Y = A\u2295B<\/strong><\/td>\nCarry Y = AB<\/strong><\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"2nd<\/p>\n

Question 12.
\nWrite the truth table and draw the timing diagram of a full adder.
\nAnswer:
\n\"2nd
\n\"2nd<\/p>\n

Question 13.
\nRealise the full adder using two half adders and a OR gate
\nAnswer:
\n\"2nd<\/p>\n

Question 14.
\nDistinguish between SOP and POS equations.
\nAnswer:
\nSOP equation is equation containing all the input variables in each of product term either in complemented or uncomplemented form.<\/p>\n

POS equation is the equation containing all the input variables either in complemented or uncomplemented form in each of sum term.<\/p>\n

Question 15.
\nConvert \\({ AB }+\\overline { { C } } \\) into canonical SOP.
\nAnswer:
\n\"2nd<\/p>\n

Question 16.
\nConvert \\((\\mathbf{A}+\\mathbf{C})(\\mathbf{B}+\\overline{\\mathbf{C}})\\) into canonical POS
\nAnswer:
\n\"2nd<\/p>\n

\"2nd<\/p>\n

Question 17.
\nDistinguish between min term and max term.
\nAnswer:
\nA max term is a special case sum term containing all input variables that make up a Boolean expression. A min term is a special case product term containing all input variable that make up a Boolean expression.<\/p>\n

Question 18.
\nWrite the truth tables for 3 variable input with min term designations.
\nAnswer:
\n\"2nd<\/p>\n

Question 19.
\nExplain the necessity of elimination redundant groups in a K-map.
\nAnswer:
\nA redundant group is a group in which all the 1 s in a group are overlapped by other groups. Redundent group should be eliminated before writing simplified Boolean equation using k map. The elimination of redundant groups results in a simple logic circuit.<\/p>\n

Question 20.
\nExplain don\u2019t care condition.
\nAnswer:
\nAn output condition that may be treated as either 1 or 0 without affecting the operation is called don\u2019t care condition.<\/p>\n

When simplifying a logic expression using a K-map, a don\u2019t care condition can be treated as a 1 if it contributes to the simplification and can be treated as 0 if it does not contribute to the simplification.<\/p>\n

Question 21.
\nDistinguish between AND-OR logic and OR-AND logic.
\nAnswer:<\/p>\n\n\n\n\n\n
AND OR logic<\/strong><\/td>\nOR-AND logic<\/strong><\/td>\n<\/tr>\n
1. It is used in simlifying SOP expression.<\/td>\n1. It is used in simplifying POS expression.<\/td>\n<\/tr>\n
2. It is realised only using NAND gates.<\/td>\n2. It is realised only using NOR gates.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 22.
\nDraw the 4 variable K-map with min term designations
\nAnswer:
\n\"2nd<\/p>\n

Question 23.
\nWrite the truth table for the expression \\(\\mathbf{Y}=\\mathbf{A} \\overline{\\mathbf{B}}+\\overline{\\mathbf{A}} \\mathbf{B}\\)
\nAnswer:
\n\"2nd<\/p>\n

\"2nd<\/p>\n

Question 24.
\nDraw the AND-OR logic circuit for the expression \\(\\mathbf{Y}=\\overline{\\mathbf{A}} \\mathbf{B}+\\overline{\\mathbf{B}}\\)
\nAnswer:
\n\"2nd<\/p>\n

Question 25.
\nDraw the logic circuit for the expression\u00a0 \\(\\mathbf{Y}=\\mathbf{A} \\mathbf{C}+\\overline{\\mathbf{C}}\\) using only basic gates.
\nAnswer:
\n\"2nd<\/p>\n

Question 26.
\nDraw the logic circuit for the expression \\(\\mathbf{Y}=\\mathbf{A} \\mathbf{B}+\\overline{\\mathbf{B}}\\) using only NAND gates
\nAnswer:
\n\"2nd<\/p>\n

Question 27.
\nDistinguish between combinational and sequential logic circuits.
\nAnswer:
\nCombinational logic circuits are circuits whose output level at any instant of time is dependent only on present levels of inputs at that time. These circuits do not have memory.<\/p>\n

Sequential logic circuits are those circuits whose output levels at any instant of time depend not only on the present input state but also on previous input states. These circuits have memory.<\/p>\n

Question 28.
\nDistinguish between SR and JK flip flop.
\nAnswer:<\/p>\n\n\n\n\n\n
\u00a0 SR Flip Flop<\/strong><\/td>\nJK Flip Flop<\/strong><\/td>\n<\/tr>\n
1. When S = R = 1, it is in forbidden state.<\/td>\n1.When J=-K= 1, it toggles.<\/td>\n<\/tr>\n
2. It can not be used for any application.<\/td>\n2. It can be used in most of applications.<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 29.
\nWhat is race around condition? How is it etiminated?
\nAnswer:
\nToggling of the output more than once during the same clock pulse is called race around condition. It can be eliminated using an RC network (edge triggering) at the clock input or by using Master-slave JK flip flop.<\/p>\n

Question 30.
\nMention the types of shift registers.
\nAnswer:<\/p>\n

    \n
  • Serial-in, serial-out.<\/li>\n
  • Serial-in, parallel-out<\/li>\n
  • Parallel-in, serial-out.<\/li>\n
  • Parallel-in, parallel-out.<\/li>\n<\/ul>\n

    Question 31.
    \nDraw the logic diagram of SISO shift register.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 32.
    \nDraw the logic diagram of SIPO shift registor
    \nAnswer:
    \n\"2nd<\/p>\n

    \"2nd<\/p>\n

    Question 33.
    \nDraw the logic diagram of PISO shift register.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 34.
    \nDraw the logic diagram PIPO shift register
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 35.
    \nMention a broad classification of counters.
    \nAnswer:
    \nCounters are classified as synchronous counters and asynchronous counters.<\/p>\n

    2nd PUC Electronics Digital Electronics Three Marks Questions and Answers<\/h3>\n

    Question 1.
    \nWhat is an XOR gate? Realise logic expression Y=A\u2295B\u2295C using 2 input two XOR gates.
    \nAnswer:
    \nXOR gate is a logic circuit whose output is HIGH only when odd number of inputs are HIGH.
    \n\"2nd<\/p>\n

    Question 2.
    \nConstruct an XOR gate Using only NAND gates and write the Boolean expression at the output of each gate.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 3.
    \nWrite the table of 2-4-2-1 code and show that it is a self complementing code
    \nAnswer:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
    Decimal Digit<\/strong><\/td>\n2-4-2-1 Code<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n0000<\/td>\n<\/tr>\n
    1<\/td>\n0001<\/td>\n<\/tr>\n
    2<\/td>\n0010<\/td>\n<\/tr>\n
    3<\/td>\n0011<\/td>\n<\/tr>\n
    4<\/td>\n0100<\/td>\n<\/tr>\n
    5<\/td>\n0101<\/td>\n<\/tr>\n
    6<\/td>\n0.100<\/td>\n<\/tr>\n
    7<\/td>\n1101<\/td>\n<\/tr>\n
    8<\/td>\n1110<\/td>\n<\/tr>\n
    9<\/td>\n1111<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    1’s complement of 1100(610<\/sub>) = 0011 = 310
    \n<\/sub>= 9’s complement of 6
    \n\u2234 2421 code is self complementing code<\/p>\n

    \"2nd<\/p>\n

    Question 4.
    \nWrite ASCII codes for decimal numbers 0 and 9
    \nAnswer:<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n
    Decimal Number<\/strong><\/td>\nASCIlCode<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n48<\/td>\n<\/tr>\n
    1<\/td>\n49<\/td>\n<\/tr>\n
    2<\/td>\n50<\/td>\n<\/tr>\n
    3<\/td>\n51<\/td>\n<\/tr>\n
    4<\/td>\n52<\/td>\n<\/tr>\n
    5<\/td>\n53<\/td>\n<\/tr>\n
    6<\/td>\n54<\/td>\n<\/tr>\n
    7<\/td>\n55<\/td>\n<\/tr>\n
    8<\/td>\n56<\/td>\n<\/tr>\n
    9<\/td>\n57<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 5.
    \nDraw logic symbol, timing diagram and truth table of
    \n(i) Half adder
    \n(ii) Half subtractor.
    \nAnswer:
    \n(i) Half adder
    \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
    Inputs<\/strong><\/td>\nSum\u00a0<\/strong><\/td>\nCarry<\/strong><\/td>\n<\/tr>\n
    A<\/strong><\/td>\nB<\/strong><\/td>\nY = A +B<\/strong><\/td>\nY = AB<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    (ii) Half subtractor.
    \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
    Inputs<\/strong><\/td>\nOutputs<\/strong><\/td>\n<\/tr>\n
    A<\/strong><\/td>\nB<\/strong><\/td>\nDifference<\/strong><\/td>\nBorrow<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n1<\/td>\n0<\/span><\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 6.
    \nRealise the half adder using only NAND gates and write the Boolean expression at the output of each gate.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 7.
    \nWrite the truth table and draw the timing diagram of full adder.
    \nAnswer:<\/p>\n\n\n\n\n\n\n\n\n
    Inputs<\/strong><\/td>\nOutputs<\/strong><\/td>\n<\/tr>\n
    A<\/strong><\/td>\nB<\/strong><\/td>\nSum Y = A + B<\/strong><\/td>\nCarry Y = AB<\/strong><\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    \"2nd<\/p>\n

    Question 8.
    \nRealise full adder using two XOR, two AND gates and an OR gate.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 9.
    \nWrite A+BC+AB into its canonical SOP and write the expression in min term designation.
    \nAnswer:
    \n\"2nd<\/p>\n

    \"2nd<\/p>\n

    Question 10.
    \nSimplify the Boolean expression Y=\u2211m(0,2,4,6,8,10,ll,12,14,15) +\u2211d(9,13) using k-map.
    \nAnswer:
    \n\"2nd<\/p>\n

    Question 11.
    \nList the different types of flip flops.
    \nAnswer:<\/p>\n

      \n
    • SR flip flop<\/li>\n
    • D flip flop<\/li>\n
    • JKflip flop<\/li>\n
    • Master-Slave JK flip flop.<\/li>\n<\/ul>\n

      Question 12.
      \nDraw the logic symbol, truth table and timing diagram of D flip flop.
      \nAnswer:
      \n\"2nd<\/p>\n

      Question 13.
      \nDraw the logic symbol, truth table and timing diagram of T flip flop
      \nAnswer:
      \n\"2nd
      \n\"2nd<\/p>\n

      Question 14.
      \nMention few applications of flip flops.
      \nAnswer:<\/p>\n

        \n
      • Transfer and storage of data.<\/li>\n
      • Frequency division.<\/li>\n
      • Counters<\/li>\n
      • Detection of input sequence of data.<\/li>\n<\/ul>\n

        Question 15.
        \nWrite truth table, timing diagram and logic diagram of SISO register.
        \nAnswer:
        \n\"2nd<\/p>\n

        Question 16.
        \nDraw the logic diagram and counting sequence of a four bit synchronous up counter.
        \nAnswer:
        \n\"2nd
        \n\"2nd<\/p>\n

        2nd PUC Electronics Digital Electronics Five Marks Questions and Answers<\/h3>\n

        Question 1.
        \nExplain the universal property of NAND gate and realize AND, OR, NOT and XOR gates with their respective truth tables.
        \nAnswer:
        \nNAND is called universal gate because other logic gates can be realised using NAND gates.
        \n(1) AND gate from NAND gates:
        \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
        Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
        A<\/strong><\/td>\nB<\/strong><\/td>\nY = AB<\/strong><\/td>\n<\/tr>\n
        0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
        0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
        1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
        1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        (2) OR gate from NAND gates:
        \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
        Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
        A<\/strong><\/td>\nB<\/strong><\/td>\nY =A+B<\/strong><\/td>\n<\/tr>\n
        0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
        0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        (3) NOT gate from NAND gate:
        \nAnswer:
        \n\"2nd<\/p>\n\n\n\n\n\n\n
        Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
        A<\/td>\n\\(\\overline{\\mathbf{A}}\\)<\/td>\n<\/tr>\n
        0<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        (4) XOR gate from NAND gates:
        \nAnswer:
        \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
        Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
        A<\/td>\n\u00a0B<\/td>\nY<\/td>\n<\/tr>\n
        0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
        0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        \"2nd<\/p>\n

        Question 2.
        \nWhat is a half subtractor? Explain its working with a truth table, logic diagram and timing diagram.
        \nAnswer:
        \nHalf subtractor is a logic circuit which subtracts two bits and gives difference and borrow.
        \n\"2nd
        \n\"2nd<\/p>\n\n\n\n\n\n\n\n\n
        Inputs<\/strong><\/td>\nOutput<\/strong><\/td>\n<\/tr>\n
        A<\/strong><\/td>\nB<\/strong><\/td>\nDifference<\/strong><\/td>\nBorrow<\/strong><\/td>\n<\/tr>\n
        0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
        0<\/td>\n1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
        1<\/td>\n0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
        1<\/td>\n1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

        Question 3.
        \nWhat is full adder? Explain its working with respect to three input XOR gate and basic gates with the help of truth table and Boolean expression.
        \nAnswer:
        \nFull adder is a combinational logic circuit that performs arithmetic sum of three bits and gives their sum and carry.
        \n\"2nd<\/p>\n

        Question 4.
        \nSimplify the Boolean expression Y=Em(0,4,5,7) using k-map. Realise simplified expression by using both AND-OR logic and NAND-NAND gates.
        \nAnswer:
        \n\"2nd<\/p>\n

        Question 5.
        \nConvert \\(Y\\quad =\\bar { AB } +BC+\\bar { BD } \\) into its canonical SOP form and write the truth table for the corresponding min term designation.
        \nAnswer:
        \n\"2nd<\/p>\n

        Question 6.
        \nWith a logic circuit, explain working of un-clocked SR flip flop built using NAND gates. Draw its timing diagram and truth table.
        \nAnswer:
        \n\"2nd
        \nIt is constructed using inverters inserted into inputs of cross coupled NAND gates.
        \nWorking:<\/p>\n

          \n
        1. When S=0, R=0, it does not respond and hence outputs Q and Q will remain in their previous state. This is called HOLD condition.<\/li>\n
        2. When S=1 and R=0, the output Q and Q change to 1 and 0. This condition is called SET state.<\/li>\n
        3. When S=0, R=1, the output Q and Q change to 0 and 1. This condition is called RESET state.<\/li>\n
        4. When S=1 and R=l, it drives output Q and Q both to HIGH which is FORBIDDEN or INVALID condition.<\/li>\n<\/ol>\n

          \"2nd<\/p>\n

           <\/p>\n

          Question 7.
          \nExplain the working of clocked Jk flip flop with its logic diagram ,truth table and timing
          \nAnswer:<\/p>\n

          \"2nd<\/p>\n

            \n
          1. When J = 0, K= 0, the S and R inputs are both at 0 and hence the output is in the HOLD state.<\/li>\n
          2. When J = 0, K = 1, S input is at 0 while R can be either at 0 or 1, but output is always in the RESET state.<\/li>\n
          3. When J = 1, K = 0, S input can be 0 or 1 but R input is always at logic 0 and hence the output remains at a stable SET state.<\/li>\n
          4. When J = 1, K = 1 the Flip flop goes to complementary’ state of previous output i.e, flip flop toggles<\/li>\n<\/ol>\n

            \"2nd<\/p>\n

             <\/p>\n

             <\/p>\n

            \"2nd<\/p>\n

            Question 8.
            \nExplain the working of SISO shift register with relevant diagrams.
            \nAnswer:<\/p>\n

            \"2nd<\/p>\n

            With four SR flip flops it can store upto 4 bits of data. Serial data is applied to S input of the first flip flop.<\/p>\n

            When serial data is transferred into the register, each new bit is clocked into first flip flop at the positive edge of each clock pulse. The bit that was stored by first flip flop is transferred to second flip flop and so on.<\/p>\n

            The shifting out of stored data 0101 serially from the register requires four clock pulses, which is represented as in the following truth table.<\/p>\n

            Question 9.
            \nExplain the working of a four bit synchronous up counter using relevant diagrams.
            \nAnswer:
            \n\"2nd
            \nCounter is a logic circuit used for counting the pulses. It is a set of flip flops whose state changes in response to pulses applied to their inputs.<\/p>\n

            Counters are of two types:<\/p>\n

              \n
            • Synchronous counters and<\/li>\n
            • Asynchronous counters.<\/li>\n<\/ul>\n

              \"2nd
              \nIn a synchronous circuit, the clock signal is applied to all flip flops simultaneously.<\/p>\n

              Question 10.
              \nSimplify the Boolean equation Y=\u2211m(0,2,4,8,10) +\u2211d(12,14) using K-map. Draw the NAND gate equivalent circuit to realise simplified equation.
              \nAnswer:
              \n\u2211m(0,2,4,8,10) +\u2211d(12,14)<\/p>\n

              \"2nd<\/p>\n

              Question 11.
              \nSimplify the Boolean equation Y= \u2211m(4,5,7,9,11,12,13,15) +\u2211d(1,3,8) using k-map. Draw the NAND gate equialent circuit to realise the simplified equation.
              \nAnswer:
              \nY=\u2211d_(4,5,7,9,11,12,13,15) +\u2211d (1,3,8)
              \n\\(Y=B \\bar{C}+D\\)<\/p>\n

              \"2nd<\/p>\n

              Question 12.
              \nSimplify Boolean equation Y=\u2211d (0,2,6,8,10,12,14) +\u2211d (4,9,13) using K map. Draw the NAND gate equivalent circuit to realise simplified equation.
              \nAnswer:
              \nY=\u2211d (0,2,6,8,10,12,14) +\u2211d (4,9,13)<\/p>\n

              \"2nd
              \n\"2nd
              \nNAND gate equivalent circuit.<\/p>\n

              Question 13.
              \nSimplify Boolean equation Y=\u2211d (1,3,5,6,8,9,11,12) +\u2211d (,0,7,1) K map.
              \nAnswer:<\/p>\n

              \"2nd<\/p>\n","protected":false},"excerpt":{"rendered":"

              Students can Download 2nd PUC Electronics Chapter 10 Digital Electronics Questions and Answers, Notes Pdf, 2nd PUC Electronics Question Bank with Answers\u00a0helps you to revise the complete Karnataka State Board Syllabus and score more marks in your examinations. Karnataka 2nd PUC Electronics Question Bank Chapter 10 Digital Electronics 2nd PUC Electronics Digital Electronics One Mark …<\/p>\n","protected":false},"author":5,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[82],"tags":[],"jetpack_sharing_enabled":true,"jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts\/24457"}],"collection":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/comments?post=24457"}],"version-history":[{"count":0,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts\/24457\/revisions"}],"wp:attachment":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/media?parent=24457"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/categories?post=24457"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/tags?post=24457"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}