{"id":12656,"date":"2019-12-17T15:26:46","date_gmt":"2019-12-17T09:56:46","guid":{"rendered":"https:\/\/kseebsolutions.guru\/?p=12656"},"modified":"2021-07-02T15:36:30","modified_gmt":"2021-07-02T10:06:30","slug":"2nd-puc-computer-science-question-bank-chapter-3","status":"publish","type":"post","link":"https:\/\/kseebsolutions.guru\/2nd-puc-computer-science-question-bank-chapter-3\/","title":{"rendered":"2nd PUC Computer Science Question Bank Chapter 3 Logic Gates"},"content":{"rendered":"

You can Download Chapter 3 Logic Gates Questions and Answers, Notes, 2nd PUC Computer Science Question Bank with Answers<\/a> Karnataka State Board Solutions help you to revise complete Syllabus and score more marks in your examinations.<\/p>\n

Karnataka 2nd PUC Computer Science Question Bank Chapter 3 Logic Gates<\/h2>\n

2nd PUC Computer Science Logic Gates One Mark Questions and Answers<\/h3>\n

Question 1.
\nWhat is a logic gate?
\nAnswer:
\nIt is an electronic circuit having one or more than one input and only one output.<\/p>\n

Question 2.
\nMention the three basic logic gates.
\nAnswer:
\nThe three basic logic gates are NOT, OR and AND gate.<\/p>\n

\"KSEEB<\/p>\n

Question 3.
\nWhich basic gate is named as Inverter?
\nAnswer:
\nThe NOT gate is named as Inverter.<\/p>\n

Question 4.
\nWhich are the three logic operations?
\nAnswer:
\nThe three logic operations are Nor, Or and And.<\/p>\n

Question 5.
\nWrite the standard symbol for AND gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 6.
\nWrite the truth table for AND gate.
\nAnswer:<\/p>\n\n\n\n\n\n\n\n
A<\/td>\nB<\/td>\nY = A.B<\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 7.
\nWrite the logic circuit for AND gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 8.
\nWrite the standard symbol for OR gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 9.
\nWrite the truth table for OR gate.
\nAnswer:<\/p>\n\n\n\n\n\n\n\n
A<\/td>\nB<\/td>\n\u00a0Y = A+B<\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

\"KSEEB<\/p>\n

Question 10.
\nWrite the logic circuit for OR gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 11.
\nWrite the standards symbol for NOT gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 12.
\nWrite the truth table for NOT gate.
\nAnswer:<\/p>\n\n\n\n\n\n
A<\/td>\nY = A’<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 13.
\nWrite the logic circuit for NOT gate.
\nAnswer:
\n\"2nd<\/p>\n

Question 14.
\nWhat is a truth table?
\nAnswer:
\nA table that represents all possible values of logical variables along with all the possible results of the given combinations of values.<\/p>\n

Question 15.
\nWhat is meant by universal gates?
\nAnswer:
\nA gate which can be used to create any Logic gate is called Universal Gate.<\/p>\n

Question 16.
\nMention different universal gates.
\nAnswer:
\nThe different universal gates are NAND and NOR.<\/p>\n

\"KSEEB<\/p>\n

Question 17.
\nWhat is the output of the two-input NAND gate for the inputs: A=0, B=1?
\nAnswer:
\nThe output of the two-input NAND gate for the input A=0, B=1 is 1.<\/p>\n

Question 18.
\nWhat are the values of the inputs to a three-input NAND gate, if its output is 1?
\nAnswer:
\n\"2nd<\/p>\n

Question 19.
\nWhat are the values of the inputs to a three-input NAND gate, if its output is 0?
\nAnswer:<\/p>\n\n\n\n\n
X<\/td>\nY<\/td>\nz<\/td>\n(XYZ)’<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 20.
\nWhat is the output of the two-input OR gate for the inputs: A=0, B=0?
\nAnswer:
\nThe output of the two-input OR gate for the inputs A=0, B=0 is 0.<\/p>\n

Question 21.
\nWhat are the values of the inputs to a three-input OR gate, if its output is 0?
\nAnswer:<\/p>\n\n\n\n\n
X<\/td>\nY<\/td>\nz<\/td>\nY=X+Y+Z<\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Question 22.
\nWhat are the values of the inputs to a three-input OR gate, if the output is 1?
\nAnswer:
\n\"2nd<\/p>\n

Question 23.
\nFor the truth table given below, what type of logic gate does the output X represent?
\n\"2nd
\nAnswer:
\nThe type of logic gate that the output X represent is NAND.<\/p>\n

Question 24.
\nFor the truth table given below, what type of logic gate does the output X represent?<\/p>\n\n\n\n\n\n\n\n
A<\/td>\nB<\/td>\nX<\/td>\n<\/tr>\n
0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
1<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Answer:
\nThe logic gate XOR generates the output mentioned in the above truth table.<\/p>\n

Question 25.
\nState the principle duality of theorems in Boolean algebra.
\nAnswer:
\nThe principle of duality theorems states that starting with a Boolean relation another Boolean relation can be derived by.<\/p>\n

    \n
  1. Changing each OR sign (+) to and AND sign (.)<\/li>\n
  2. Changing each AND sign (.) to an OR sign (+)<\/li>\n
  3. Changing each 0 by 1 and each 1 by 0.<\/li>\n<\/ol>\n

    2nd PUC Computer Science Logic Gates Three Marks Questions and Answers<\/h3>\n

    Question 1.
    \nWhat is meant by proof by perfect induction? Give an example.
    \nAnswer:
    \nIt is a method of proving Boolean theorems by substituting all possible values of the variables. The possible values of the variables are 0 and 1.
    \nFor example, 0 + X = X
    \nIf X = 0, then LHS = 0 + X
    \n= 0 + 0
    \n= 0
    \nIf X = 1, then LHS = 0 + X
    \n= 0 + 1
    \n= 1<\/p>\n

    Question 2.
    \nWrite the truth table and standard symbol of AND gate.
    \nAnswer:
    \nThe standard symbol of AND gate is
    \n\"2nd
    \nThe truth table of AND (Y=A.B)<\/p>\n\n\n\n\n\n\n\n
    A<\/td>\nB<\/td>\nY = A.B<\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    \"KSEEB<\/p>\n

    Question 3.
    \nWrite the AND gate rule. (Write the output conditions)
    \nAnswer:
    \nThe AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.<\/p>\n\n\n\n\n\n\n\n
    A<\/td>\nB<\/td>\nY=A.B<\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 4.
    \nWrite the truth table and the standard symbol of the OR gate.
    \nAnswer:
    \nThe standard symbol of the OR gate.
    \n\"2nd
    \nThe truth table for the OR gate.<\/p>\n\n\n\n\n\n\n\n
    A<\/td>\nB<\/td>\nY=A+B<\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 5.
    \nWrite the OR gate rule, (write the output conditions)
    \nAnswer:
    \nThe OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.<\/p>\n\n\n\n\n\n\n\n
    A<\/td>\nB<\/td>\nY=A+B<\/td>\n<\/tr>\n
    0<\/td>\n0<\/td>\n0<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n1<\/td>\n1<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 6.
    \nWrite the truth table and standard symbol of NOT gate.
    \nAnswer:
    \nThe truth table of NOT<\/p>\n\n\n\n\n\n
    A<\/td>\nY=A’<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    The standard symbol of NOT gate.
    \n\"2nd<\/p>\n

    Question 7.
    \nWrite the NOT gate rule, (write the output conditions)
    \nAnswer:
    \nThe NOT gate is an electronic circuit that produces an inverted version of the input as its output. It is also known as an inverter.<\/p>\n\n\n\n\n\n
    A<\/td>\nY=A’<\/td>\n<\/tr>\n
    0<\/td>\n1<\/td>\n<\/tr>\n
    1<\/td>\n0<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

    Question 8.
    \nWrite the truth table and standard symbol of NAND gate.
    \nAnswer:
    \nThe truth table of NAND gate
    \n\"2nd
    \nThe standard symbol of NAND gate.
    \n\"2nd<\/p>\n

    Question 9.
    \nExplain the working of NAND gate, (write the output conditions)
    \nAnswer:
    \nThis is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low.
    \n\"2nd<\/p>\n

    Question 10.
    \nWrite the truth table and standard symbol of NOR gate.
    \nAnswer:
    \nThe truth table of NOR gate
    \n\"2nd
    \nThe standard symbol of NOR gate
    \n\"2nd<\/p>\n

    Question 11.
    \nExplain the working of NOR gate, (write the output conditions)
    \nAnswer:
    \nThis is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high.
    \n\"2nd<\/p>\n

    Question 12.
    \nDraw the logic gate diagram to implement AND and OR gates using NAND gates only, (any two gates)
    \nAnswer:
    \nImplementing AND using NAND gates
    \n\"2nd
    \nImplementing OR using NAND gates
    \n\"2nd<\/p>\n

    \"KSEEB<\/p>\n

    Question 13.
    \nDraw the logic gate diagram to implement AND and OR gates using NOR gates only. (Any two gates).
    \nAnswer:
    \nImplementing AND using NOR gates
    \n\"2nd
    \nImplementing OR using NOR gates
    \n\"2nd<\/p>\n

    Question 14.
    \nDraw the logic gate diagram to implement NOT using<\/p>\n

      \n
    1. Only NOR gates<\/li>\n
    2. Only NAND gates.<\/li>\n<\/ol>\n

      Answer:
      \nThe logic gate diagram to implement NOT using only NOR gates
      \n\"2nd
      \nThe logic gate diagram to implement NOT using only NAND gates
      \n\"2nd<\/p>\n

      Question 15.
      \nState De Morgan’s theorems.
      \nAnswer:
      \n1. De Morgan’s theorem 1:
      \nWhen the OR sum of two variables is inverted, this is the same as. inverting each variable individually and then ANDing these inverted variables.
      \n(X + Y)’ = X’. Y’<\/p>\n

      2. De Morgan’s theorem 2:
      \nWhen the AND product of two variables is inverted, this is the same as inverting each variable individually and then ORing them.
      \n(X.Y)’ = X’ + Y’<\/p>\n

      Question 16.
      \nWhat is the principle of duality? Give an example.
      \nAnswer:
      \nThe principle of duality states that starting with a Boolean relation, another relation can be derived by<\/p>\n

        \n
      1. Changing each OR sing (+) to an AND sign (.)<\/li>\n
      2. Changing each AND sing (.) to an OR sign (+).<\/li>\n
      3. Replacing each 0 by 1 and each 1 by 0.<\/li>\n
      4. All variables are complemented.<\/li>\n<\/ol>\n

        For example, (X + Y’) dual is (X’. Y)<\/p>\n

        Question 17.
        \nGive the dual form of (any two)<\/p>\n

          \n
        1. 0.X + X.Y + 1.X<\/li>\n
        2. X.(Y+Z) = X.Y + X.Z<\/li>\n
        3. X + X’.Y = X + Y<\/li>\n
        4. 1 + X = 1<\/li>\n<\/ol>\n

          Answer:
          \nThe dual form of<\/p>\n

            \n
          1. 0.X + X.Y + 1.X\u00a0 \u00a0is 1 + X’. X’ + Y’. 0 + X’<\/li>\n
          2. X.(Y+Z) = X.Y + X.Z\u00a0 is\u00a0 X’ + (Y’.Z’) = X’ + Y’. X’ + Z’<\/li>\n
          3. X + X’.Y = X + Y\u00a0 is\u00a0 X’. X + Y’ = X’. Y’<\/li>\n
          4. 1 + X = 1\u00a0 is\u00a0 0.X = X.<\/li>\n<\/ol>\n

            \"KSEEB<\/p>\n

            Question 18.
            \nSimplify the following logical expression using De Morgan’s theorems.
            \nAnswer:
            \n1. (A + B).C
            \n= AC + BC.<\/p>\n

            2. (A + BC). (D + EF)
            \n(A + BC) . D + (A + BC). EF
            \nAD + BCD + AEF + BCEF.<\/p>\n

            Question 19.
            \nPrepare the truth of combinations for the following Boolean algebra expressions.
            \nAnswer:
            \n1. AB’C’ + A’B
            \n\"2nd<\/p>\n

            2. A’B’C’ + AC + AB
            \n\"2nd<\/p>\n

            3. XZ + XY’ + X’Z
            \n\"2nd<\/p>\n

            Question 20.
            \nProve the following rules using the proof by perfect induction.<\/p>\n

              \n
            1. XY’ + XY = X<\/li>\n
            2. X+Y=Y+X<\/li>\n<\/ol>\n

              Answer:
              \n1. XY’ + XY = X
              \nBy proof of perfect induction X = 0, Y =1
              \nXY’ + XY = X
              \nLHS = 0.0 + 0.1 = 0 + 0 = 0
              \nBy proof of perfect induction X = 1, Y = 0
              \nLHS = 1.1 + 1.0 = 1 + 0 = 1.<\/p>\n

              2. X + Y = Y + X
              \nBy proof of perfect induction X = 0, Y = 1
              \nLHS = 0 + 1 = 1
              \nRHS = 1 + 0=1
              \nLHS = RHS
              \nBy proof of perfect induction X = 1, Y = 0
              \nLHS = 1 + 0 = 1
              \nRHS = 0 + 1 = 1
              \nLHS = RHS<\/p>\n

              Question 21.
              \nDraw logic circuit diagram for the following expressions.
              \nAnswer:
              \n1. Y = AB + B’C + (CA)’
              \n\"2nd
              \n2. Y = (XY)’ + ZX’ + Y’Z
              \n\"2nd<\/p>\n

              Question 22.
              \nSimplify the following Boolean expressions.
              \n\"2nd
              \nAnswer:
              \n\"2nd<\/p>\n

              Question 23.
              \nComplement the following expressions and simplify.
              \n\"2nd
              \nAnswer:
              \n\"2nd<\/p>\n","protected":false},"excerpt":{"rendered":"

              You can Download Chapter 3 Logic Gates Questions and Answers, Notes, 2nd PUC Computer Science Question Bank with Answers Karnataka State Board Solutions help you to revise complete Syllabus and score more marks in your examinations. Karnataka 2nd PUC Computer Science Question Bank Chapter 3 Logic Gates 2nd PUC Computer Science Logic Gates One Mark …<\/p>\n","protected":false},"author":5,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[82],"tags":[],"jetpack_sharing_enabled":true,"jetpack_featured_media_url":"","_links":{"self":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts\/12656"}],"collection":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/comments?post=12656"}],"version-history":[{"count":0,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/posts\/12656\/revisions"}],"wp:attachment":[{"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/media?parent=12656"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/categories?post=12656"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/kseebsolutions.guru\/wp-json\/wp\/v2\/tags?post=12656"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}